A Dynamic Fault Classification Scheme

In this paper, we introduce a novel and simple fault rate classification scheme in hardware. It is based on the well-known threshold scheme, counting ticks between faults. The innovation is to introduce variable threshold values for the classification of fault rates and a fixed threshold for permanent faults. In combination with field data obtained from 9728 processors of a SGI Altix 4700 computing system, a proposal for the frequency-over-time behavior of faults results, experimentally justifying the assumption of dynamic and fixed threshold values. A pattern matching classifies the fault rate behavior over time. From the behavior a prediction is made. Software simulations show that fault rates can be forecast with 98 % accuracy. The scheme is able to adapt to and diagnose sudden changes of the fault rate, e.g. a spacecraft passing a radiation emitting celestial body. By using this scheme, fault-coverage and performance can be dynamically adjusted during runtime. For validation, the scheme is implemented by using different design styles, namely Field Programmable Gate Arrays (FPGAs) and standard-cells. Different design styles were chosen to cover different economic demands. From the implementation, characteristics like the length of the critical path, capacity and area consumption result. This work deals with the handling of faults after they have been detected (fault diagnosis). We do not use the fault rate for the classification of fault types such as transient, intermittent or permanent faults. We classify the current fault rate and forecast its development. On this basis the performance and fault coverage can be dynamically adjusted during runtime. We call this scheme History Voting. The rest of this work is organized as follows: in Section 2, we present and discuss observations on fault rates in real-life systems. In Section 3, we discuss related work. Section 4 introduces History Voting. We seamlessly extend the scheme to support multiple operating units used in multicore or multithreaded systems. The scheme was modeled in software and its behavior simulated under the influence of faults. Section 5 presents experimental results and resource demands from standard-cell and FPGA (Field Programmable Gate Array)implementations. Section 6 concludes the paper.